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White Electronic Designs
W3HG128M64EEU-D4
ADVANCED*
1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM
FEATURES
200-pin, Small-Outline DIMM (SO-DIMM), Raw Card "B" Fast data transfer rates: PC2-6400*, PC2-5300*, PC2-4200 and PC2-3200 Utilizes 800*, 667*, 533 and 400 Mb/s DDR2 SDRAM components VCC = VCCQ = 1.8V 0.1V VCCSPD = 1.7V to 3.6V JEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture DLL to align DQ and DQS transitions with CK Multiple internal device banks for concurrent operation Supports duplicate output strobe (RDQS/RDQS#) Programmable CAS# latency (CL): 3, 4, 5* and 6* Adjustable data-output drive strength On-Die Termination (ODT) Posted CAS# latency: 0, 1, 2, 3 and 4 Serial Presence Detect (SPD) with EEPROM 64ms: 8,192 cycle refresh Gold edge contacts Single Rank RoHS Compliant JEDEC Package option * 200 Pin (SO-DIMM) * PCB - 29.20mm (1.150") TYP
NOTE: Consult factory for availability of: * Vendor source control options * Industrial temperature option
DESCRIPTION
The W3HG128M64EEU is a 128Mx64 Double Data Rate 2 SDRAM memory module based on 1Gb DDR2 SDRAM components. The module consists of eight 128Mx8, in FBGA package mounted on a 200 pin SO-DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to change or cancellation without notice.
OPERATING FREQUENCIES
PC2-6400* Clock Speed CL-tRCD-tRP
* Consult factory for availability
PC2-5300* 333MHz 5-5-5
PC2-4200 266MHz 4-4-4
PC2-3200 200MHz 3-3-3
400MHz 6-6-6
March 2006 Rev. 0
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PIN CONFIGURATION
PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL 51 DQS2 101 A1 151 DQ42 1 VREF 2 VSS 52 DM2 102 A0 152 DQ46 53 VSS 103 VCC 153 DQ43 3 VSS 4 DQ4 54 VSS 104 VCC 154 DQ47 5 DQ0 55 DQ18 105 A10/AP 155 VSS 6 DQ5 56 DQ22 106 BA1 156 VSS 7 DQ1 57 DQ19 107 BA0 157 DQ48 8 VSS 58 DQ23 108 RAS# 158 DQ52 9 VSS 59 VSS 109 WE# 159 DQ49 10 DM0 60 VSS 110 CS0# 160 DQ53 11 DQS0# 61 DQ24 111 VCC 161 VSS 12 VSS 62 DQ28 112 VCC 162 VSS 13 DQS0 63 DQ25 113 CAS# 163 NC 14 DQ6 64 DQ29 114 ODT0 164 CK1 65 VSS 115 NC 165 VSS 15 VSS 16 DQ7 66 VSS 116 A13 166 CK1# 17 DQ2 67 DM3 117 VCC 167 DQS6# 18 VSS 68 DQS3# 118 VCC 168 VSS 19 DQ3 69 NC 119 NC 169 DQS6 20 DQ12 70 DQS3 120 NC 170 DM6 21 VSS 71 VSS 121 VSS 171 VSS 22 DQ13 72 VSS 122 VSS 172 VSS 23 DQ8 73 DQ26 123 DQ32 173 DQ50 74 DQ30 124 DQ36 174 DQ54 24 VSS 25 DQ9 75 DQ27 125 DQ33 175 DQ51 26 DM1 76 DQ31 126 DQ37 176 DQ55 27 VSS 77 VSS 127 VSS 177 VSS 28 VSS 78 VSS 128 VSS 178 VSS 29 DQS1# 79 CKE0 129 DQS4# 179 DQ56 30 CK0 80 NC 130 DM4 180 DQ60 31 DQS1 81 VCC 131 DQS4 181 DQ57 32 CK0# 82 VCC 132 VSS 182 DQ61 83 NC 133 VSS 183 VSS 33 VSS 34 VSS 84 NC 134 DQ38 184 VSS 35 DQ10 85 BA2 135 DQ34 185 DM7 36 DQ14 86 NC 136 DQ39 186 DQS7# 137 DQ35 187 VSS 37 DQ11 87 VCC 38 DQ15 88 VCC 138 VSS 188 DQS7 39 VSS 89 A12 139 VSS 189 DQ58 40 VSS 90 A11 140 DQ44 190 VSS 41 VSS 91 A9 141 DQ40 191 DQ59 42 VSS 92 A7 142 DQ45 192 DQ62 43 DQ16 93 A8 143 DQ41 193 VSS 44 DQ20 94 A6 144 VSS 194 DQ63 45 DQ17 95 VCC 145 VSS 195 SDA 46 DQ21 96 VCC 146 DQS5# 196 VSS 47 VSS 97 A5 147 DM5 197 SCL 48 VSS 98 A4 148 DQS5 198 SA0 49 DQS2# 99 A3 149 VSS 199 VCCSPD 50 NC 100 A2 150 VSS 200 SA1
W3HG128M64EEU-D4
ADVANCED
PIN NAMES
SYMBOL A0 - A13 ODT0 CK0, CK0# CK1, CK1# CKE0 CS0# RAS#, CAS#, WE# BA0 - BA2 DM0 - DM7 DQ0 - DQ63 DQS0 - DQS7 DQS0#-DQS7# SCL SA0-SA1 SDA VCC VREF VSS VCCSPD NC DESCRIPTION Address input On-Die Termination Differential Clock Inputs Differential Clock inputs Clock Enable input Chip select Command Inputs Bank Address Inputs Input Data Mask Data Input/Output Data Strobe Serial Clock for Presence Detect Presence Detect Address Inputs Serial Presence Detect Data Power Supply SSTL_18 reference voltage Ground Serial EEPROM Power Supply No Connect
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FUNCTIONAL BLOCK DIAGRAM
3 CS0# DQS0# DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1# DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2# DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3# DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
3
W3HG128M64EEU-D4
ADVANCED
DQS4# DQS4 DM4 DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5# DQS5 DM5 DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6# DQS6 DM6 DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7# DQS7 DM7 DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ
100
DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ
DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ
DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ
BA0-BA2 A0-A13 RAS# CAS# WE# CKE0 ODT0
BA0-BA2: DDR2 SDRAMs A0-A13: DDR2 SDRAMs RAS#: DDR2 SDRAMs CAS#: DDR2 SDRAMs WE#: DDR2 SDRAMs CKE0: DDR2 SDRAMs ODT0: DDR2 SDRAMs
SCL WP
Serial PD A0 A1 A2
SDA
CK0 CK0#
100
DDR2 SDRAMs x 4
SA0 SA1
CK1 CK1#
DDR2 SDRAMs x 4
VCCSPD VCC VREF VSS
Serial PD DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAMs, EEPROM
NOTE: 1. All resistor values are 22 ohm unless otherwise specified.
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Symbol VCC VIN, VOUT TSTG TCASE TOPR II Parameter VCC Supply Voltage Relative to VSS Voltage on any Pin Relative to VSS Storage Temperature DDR2 SDRAM Device Operating Temperature* Operating Temperature (Ambient) Input Leakage Current; Any input 0V VIN VCC; VREF input 0V VIN 0.95V; (All other pins not under test = 0V) Min -0.5 -0.5 -55 0 0 -40
W3HG128M64EEU-D4
ADVANCED
ABSOLUTE MAXIMUM DC CHARACTERISTICS
Max 2.3 2.3 100 85 65 40 Units V V C C C A
IOZ IVREF
Output Leakage Current; 0V VOUT VCCQ; DQs and ODT are disabled VREF Leakage Current; VREF = Valid VREF level
Command/Address, RAS#, CAS#, WE# S#, CKE CK, CK# DM DQ, DQS, DQS#
-20 -5 -5 -16
20 5 5 16
A A
* TCASE specifies as the temperature at the top center of the memory devices.
RECOMMENDED DC OPERATING CONDITIONS
All voltages referenced to VSS Parameter Supply Voltage I/O Reference Voltage I/O Termination Voltage (system)
NOTE: 1. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed 1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed 2 percent of VREF (DC). This measurement is to be taken at the nearest VREF bypass capacitor. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.
Symbol VCC VREF VTT
Min 1.7 0.49 x VCC VREF - 40
Max 1.9 0.51 x VCC VREF + 40
Units V V mV
Notes 1 2
CAPACITANCE
TA = 25C, f = 100MHz, VCC = 1.8V, VREF = VSS Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#,CAS#,WE#) Input Capacitance (CKE0) Input Capacitance (CK0, CK0#) Input Capacitance (CS0#) Input Capacitance (DQS0#-DQS17#) Input Capacitance (BA0-BA1) Data input/output Capacitance (DQ0-DQ63)
NOTE: * These capacitance values are based on worst case component values in conjunction with the circuit boards associated parasitic net capacitance.
Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT
Max 35 35 31 15 31 6 35 6
Unit pF pF pF pF pF pF pF pF
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DDR2 SDRAM components only VCC = +1.8V 0.1V Parameter Operating one device bank active-precharge current; Operating one device bank active-readprecharge current; Precharge power-down current; Precharge quiet standby current; Precharge standby current; Symbol Condition ICC0
W3HG128M64EEU-D4
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
806 TBD
665 800
534 640
403 640
Units mA
tCK = tCK (ICC), tRC = tRC (ICC), tRAS = tRAS MIN (ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK (ICC), tRC = tRC (ICC), tRAS = tRAS MIN (ICC), tRCD = tRCD (ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W. All device banks idle; tCK = tCK (ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. All device banks idle; tCK = tCK (ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. All device banks idle; tCK = tCK (ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. All device banks open; tCK = tCK (ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Fast PDN Exit MR[12] = 0 Slow PDN Exit MR[12] = 1
ICC1
TBD
1,160
760
760
mA
ICC2P
TBD
56
40
40
mA
ICC2Q
TBD
480
328
280
mA
ICC2N
TBD
520
360
280
mA
Active power-down current;
TBD TBD
320 80
240 80
200 80
mA mA
ICC3P
Active standby current;
ICC3N
All device banks open; tCK = tCK(ICC), tRAS = tRAS MAX (ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. All device banks open, Continuous burst writes; BL = 4, CL = CL (ICC), AL = 0; tCK = tCK (ICC), tRAS = tRAS MAX (ICC), tRP = tRP (ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. All device banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (ICC), AL = 0; tCK = tCK (ICC), tRAS = tRAS MAX (ICC), tRP = tRP (ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. tCK = tCK (ICC); Refresh command at every tRFC (ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (ICC), AL = tRCD (ICC)-1 x tCK (ICC); tCK = tCK (ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING
TBD
560
400
320
mA
Operating burst write current;
ICC4W
TBD
1,440
1,040
960
mA
Operating burst read current;
ICC4R
TBD
1,640
1,160
1,080
mA
Burst refresh current;
ICC5
TBD
2,160
2,000
1,920
mA
Self refresh current;
ICC6
TBD
56
40
40
mA
Operating device bank interleave read current;
ICC7
TBD
2,720
2,360
2,360
mA
Note: * ICC specification is based on MICRON components. Other DRAM manufacturers specification may be different.
March 2006 Rev. 0
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AC OPERATING CONDITIONS
VCC = +1.8V 0.1V AC Characteristics Parameter CL = 6 Clock Clock cycle time CL = 5 CL = 4 CL = 3 CK high-level width CK low-level width Half clock period Symbol
t t t t
W3HG128M64EEU-D4
ADVANCED
806 Min Max Min -
665 Max Min -
534 Max Min -
403 Max -
Units ps ps ps ps
t t
Notes
CK (6) CK (5) CK (4) CK (3) CHAVG CLAVG
t
3,000 8,000
3,000 8,000 3,000 8,000 0.48 0.48 MIN
(tCH,tCL)
t t t
3,000 8,000 3,750 8,000 3,750 8,000 5,000 8,000 0.52 0.52 5,000 8,000 5,000 8,000 5,000 8,000 0.48 0.48 MIN
(tCH,tCL)
t t
16, 22, 36, 38
t
0.52 0.52
0.48 0.48 MIN
(tCH,tCL)
t
0.52 0.52
0.48 0.48 MIN
(tCH,tCL)
t t
0.52 0.52
CK CK
t
45 46
HP
ps
Absolute tCk Clock (Absolute)
t
CKabs
CKAVG+ CKAVG+ CKAVG+ CKAVG+ CKAVG+ CKAVG+ CKAVG+ CKAVG+ (MIN)+ (MAX)+ (MIN)+ (MAX)+ (MIN)+ (MAX)+ (MIN)+ (MAX)+ t t t t t t t t JITPER JITPER JITPER JITPER JITPER JITPER JITPER JITPER (MIN) (MAX) (MIN) (MAX) (MIN) (MAX) (MIN) (MAX)
t t t t t t t t
ps
Absolute CK high-level width
t
CHabs
CKAVG CKAVG CKAVG CKAVG CKAVG CKAVG CKAVG CKAVG t t t t t t t t (MIN)* CH (MAX)* CH (MIN)* CH (MAX)* CH (MIN)* CH (MAX)* CH (MIN)* CH (MAX)* CH t t t t t t t t AVG+ JIT AVG+ JIT AVG+ JIT AVG+ JIT AVG+ JIT AVG+ JIT AVG+ JIT AVG+ JIT DTY(MIN) DTY(MAX) DTY(MIN) DTY(MAX) DTY(MIN) DTY(MAX) DTY(MIN) DTY(MAX) CKAVG (MIN)* t CLAVG t (MIN)+ JIT DTY(MIN)
t
ps
Absolute CK low-level width
t
CLabs
CKAVG t CKAVG t CKAVG t CKAVG CKAVG CKAVG CKAVG (MAX)* (MAX)* (MAX)* (MAX)* (MIN)* t (MIN)* t (MIN)* t t CLAVG t CLAVG t CLAVG t CLAVG CLAVG CLAVG CLAVG (MAX)+ (MAX)+ (MAX)+ (MAX)+ t t t (MIN)+ JIT t (MIN)+ JIT t (MIN)+ JIT t t JIT JIT JIT JIT DTY(MIN) DTY(MIN) DTY(MIN) DTY(MIN) DTY(MIN) DTY(MIN) DTY(MIN)
t
t
t
t
ps
Clock jitter - period Clock jitter - half period Clock jitter - cycle to cycle Clock jitter Cumulative jitter error, 2 cycles Cumulative jitter error, 3 cycles Cumulative jitter error, 4 cycles Cumulative jitter error, 5cycles Cumulative jitter error, 6-10 cycles Cumulative jitter error, 11-50 cycles
t t t t t t t
t
JITPER
t
-125 -125 250 -175 -225 -250 -250
125 125 175 225 250 250 350 450
-125 -125 250 -175 -225 -250 -250 -350 -450
125 125 175 225 250 250 350 450
-125 -125 250 -175 -225 -250 -250 -350 -450
125 125 175 225 250 250 350 450
-125 -150 250 -175 -225 -250 -250 -350 -450
125 150 175 225 250 250 350 450
ps ps ps ps ps ps ps ps ps
39 40 41 42 42 42 42, 48 42, 48 42
JITDUTY JITCC
ERR2per ERR3per ERR4per ERR5per
ERR6-10per -350
ERR11-50per -450
Note: * AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
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VCC = +1.8V 0.1V AC Characteristics Parameter DQ output access time from CK/CK# Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS Data DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS DQ and DM input pulse width (for each input) Data hold skew factor DQ-DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW) DQS input high pulse width Data Strobe DQS input low pulse width DQS output access time from CK/CK# DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time
t t t t t
W3HG128M64EEU-D4
ADVANCED
AC OPERATING CONDITIONS (continued)
Symbol
t
806 Min -450
t t t
665 Min -450
t t t
534 Min -500
t t t
403 Min -600
t t t
Max 340 +450
AC (MAX)
Max 340 +450
AC (MAX)
Max 400 +500
AC (MAX)
Max 450 +600
AC (MAX)
Units ps ps ps ps ps ps ps ps ps
t
Notes 47 43 8, 9, 43 8, 10, 43 8, 10, 43 7, 15, 19 7, 15, 19 7, 15, 19 7, 15, 19 37 47 15, 17, 47 15, 17 37 37 40 37 37
QHS
t
AC HZ
t
LZ1 LZ2
AC (MIN) AC (MAX) AC (MIN) AC (MAX) AC (MIN) AC (MAX) AC (MIN) AC (MAX)
t
2* AC
(MIN)
t
t
AC (MAX)
2* AC
(MIN)
t
t
AC (MAX)
2* AC
(MIN)
t
t
AC (MAX)
2* AC
(MIN)
t
t
AC (MAX)
t
DSa
300 300 100 175 0.35 340
t
300 300 100 175 0.35 340
t
350 350 100 225 0.35 400
t
400 400 150 275 0.35 450
t
t
DHa DSb
t
t
DHb
DIPW
t
CK
QHS
t
ps ps ns
t t
QH
HP- QHS
t
t
HP- QHS
t t
t
HP- QHS
t t
t
HP- QHS
t t
t
DVW
QH
QH
QH
QH
- DQSQ
t
- DQSQ
- DQSQ
- DQSQ
DQSH DQSL
t t
0.35 0.35 -400 0.2 0.2 +400
0.35 0.35 -400 0.2 0.2 +400
0.35 0.35 -450 0.2 0.2 +450
0.35 0.35 -500 0.2 0.2 +500
CK CK
t
DQSCK DSS DSH
ps
t t
CK CK
Note: * AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
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VCC = +1.8V 0.1V AC Characteristics Parameter DQS-DQ skew, DQS to last DQ valid, per group, per access DQS read preamble Data Strobe DQS read postamble DQS write preamble setup time DQS write preamble DQS write postamble Positive DQS latching edge to associated clock edge Write command to first DQS latching transition Address and control input pulse width for each input Address and control input setup time Address and control input hold time Address and control input setup time Address and control input hold time CAS# to CAS# command delay ACTIVE to ACTIVE (same bank) command
t t t t
W3HG128M64EEU-D4
ADVANCED
AC OPERATING CONDITIONS (continued)
Symbol
t
806 Min Max 240 0.9 0.4 0 0.35 0.4 - 0.25 WLt
665 Min Max 240 0.9 0.4 0 0.35 0.6 0.4 WLt
534 Min Max 300 0.9 0.4 0 0.25 0.6 0.4 WLt
403 Min Max 350 0.9 0.4 0 0.25 0.6 0.4 WLt
Units ps
t
Notes 15, 17 33, 37, 43 33, 34, 37, 43 12, 13, 37 11, 37 37
DQSQ RPRE RPST
t
1.1 0.6
1.1 0.6
1.1 0.6
1.1 0.6
CK
t
t
CK
WPRES
t
ps
t
WPRE WPST DQSS
CK CK CK CK CK
t
0.6 0.25 WL+
t
t t
t
0.25 - 0.25 WL+
t
0.25 - 0.25 WL+
t
0.25 - 0.25 WL+
t
t
DQSS
DQSS
DQSS
DQSS
DQSS
DQSS
DQSS
DQSS
t
IPW
t t
0.6 400 400 200 275 2 54 7.5 12 37.5 40 7.5 15
t
0.6 400 400 200 275 2 55 7.5 15 37.5 70,000 40 7.5 15
t
0.6 500 500 250 375 2 55 7.5 15 37.5 70,000 40 7.5 15
t
0.6 600 600 350 475 2 55 7.5 15 37.5 70,000 40 7.5 15
t
37 6, 19 6, 19 6, 19 6, 19 37 31, 37 25, 37 37 28, 37 18, 31, 37 21, 25. 37 25, 37 20 25, 37 29, 37 29 37
ISa ISb
ps ps ps
t
IHa IHb
t t
CCD
t
CK
RC
(x8)
ns ns ns ns 70,000 ns ns ns ns ns ns ns
t
Command and Address
ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay Four Bank Activate period ACTIVE to PRECHARGE command Internal READ to precharge command delay Write recovery time Auto precharge write recovery + precharge time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE ALL command period LOAD MODE command cycle time
t t t
RRD RCD FAW
(x8)
t
t
RAS RTP WR
t
t t
DAL
t
WR + RP
t
WR + RP
t
WR + RP
t
WR + RP
t
WTR RP
t t
7.5 12
RP + CK
t t
7.5 15
RP + CK
t t
7.5 15
RP + CK
t t
10 15
RP + CK
t
RPA
MRD
2
2
2
2
CK
Note: * AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
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VCC = +1.8V 0.1V AC Characteristics Parameter CKE low to CK,CK# uncertainty Refresh REFRESH to ACTIVE or REFRESH to REFRESH command interval Average periodic refresh interval (commercial) Average periodic refresh interval (industrial)
t
W3HG128M64EEU-D4
ADVANCED
AC OPERATING CONDITIONS (continued)
Symbol
t
806 Min
t t
665 Min
t t
534 Min
t t
403 Min
t t
Max
t
Max
t
Max
t
Max
t
Units ns ns s s
Notes 26 14, 37 14, 37 14, 37
DELAY
t
IS + CK + IH
IS + CK + IH
IS + CK + IH
IS + CK + IH
RFC
127.5 70,000 127.5 70,000 127.5 70,000 127.5 70,000 7.8 3.9 tRFC tRFC
(MIN) + 10
t
REFI
7.8 3.9 tRFC
(MIN) + 10
7.8 3.9 tRFC
(MIN) + 10
7.8 3.9
REFIIT
Exit self refresh to non-READ command Self Refresh
t
XSNR
(MIN) + 10
ns
Exit self refresh to READ command Exit self refresh timing reference ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off
t
XSRD
t
200 tIS 2
t t
200 tIS 2
AC (MAX) t + 700)
200 tIS 2
t
200 tIS 2
t
t
CK
37 6, 27 37 23, 43 35, 37 24, 44
ISXR
ps 2
t t
t
AOND AOND AOFD
t
2
AC (MIN)
2
AC (MIN)
2
AC (MIN)
CK
t
AC (MIN)
AC (MAX) t + 700)
AC (MAX) t + 1,000)
AC (MAX) + 1,000)
ps
t
t
2.5
t t
2.5
2.5
t
2.5
2.5
t
2.5
2.5
t
2.5
CK
AOF
AC (MIN)
AC (MAX t AC (MAX t AC (MAX t AC (MAX AC (MIN) AC (MIN) AC (MIN) + 600) + 600) + 600) + 600)
t
ps
ODT
t
ODT turn-on (power-down mode)
t
AONPD
AC (MIN) t + 2,000
2 x CK + t AC (MAX) + 1,000 2.5 x
AC (MIN) t + 2,000
2 x CK + t AC (MAX) + 1,000 2.5 x
t
AC (MIN) t + 2,000
2 x CK + t AC (MAX) + 1,000 2.5 x
t
AC (MIN) t + 2,000
2 x CK + AC (MAX) + 1,000 2.5 x
t
ps
t
ODT turn-off (power-down mode)
tAOFPD
AC (MIN)
t
t
CK +
t
AC (MIN)
t
t
CK +
t
AC (MIN)
t
t
CK +
t
AC (MIN)
t
t
CK +
+ 2,000 AC (MAX) + 2,000 AC (MAX) + 2,000 AC (MAX) + 2,000 AC (MAX) + 1,000 + 1,000 + 1,000 + 1,000
ps
t t
ODT to power-down entry latency ODT power-down exit latency ODT enable from MRS command Power Down Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] Exit precharge power-down to any non-READ command. CKE minimum high/low time
t
t
ANPD AXPD
t
3 8 12 2 2 3
3 8 12 2 7 - AL 2 3
3 8 12 2 6 - AL 2 3
3 8 12 2 6 - AL 2 3
CK CK
37 37 37, 49 37 37 37 32, 37
t
MOD
ns
t
t
XARD
t t
CK
XARDS 7 - AL XP CKE
t t
CK CK
Note: * AC specification is based on MICRON components. Other DRAM manufactures specifications may be different.
March 2006 Rev. 0
9
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Notes: 1. All voltages referenced to VSS. 2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be conducted at nominal reference / supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. ODT is disabled for all measurements that are not ODT-specific. 3. Outputs measured with equivalent load:
VTT = VCCQ/2 25 Output (VOUT) Reference Point
W3HG128M64EEU-D4
ADVANCED*
15. 16. 17.
18. 19. 20.
4. AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.0V in the test environment and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The slew rate for the input signals used to test the device is 1.0V/ns for signals in the range between VIL (AC) and VIH (AC). Slew rates less than 1.0V/ns require the timing parameters to be derated as specified. 5. The AC and DC input level specifications are as defined in the SSTL_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. There are two sets of values listed for Command/Address: tISa, tIHa and tISb, tIHb. The tISa, tIHa values (for reference only) are equivalent to the baseline values of tISb, tIHb at VREF when the slew rate is 1V/ns. The baseline values, tISb, tIHb, are the JEDEC defined values, referenced from the logic trip points. tISb is referenced from VIH (AC) for a rising signal and VIL (AC) for a falling signal, while tIHb is referenced from VIL (DC) for a rising signal and VIH (DC) for a falling signal. If the Command/Address slew rate is not equal to 1 V/ns, then the baseline values must be derated. 7. The values listed are for the differential DQS strobe (DQS and DQS#) with a differential slew rate of 2 V/ns (1 V/ns for each signal). There are two sets of values listed: tDSa. tDHa and tDSb, tDHb. The tDSa, tDHa values (for reference only) are equivalent to the baseline values of tDSb, tDHb at VREF when the slew rate is 2 V/ns, differentially. The baseline values, tDSb, tDHb, are the JEDEC-defined values, referenced from the logic trip points. tDSb is referenced from VIH (AC) for a rising signal and VIL (AC) for a falling signal, while tDSb is referenced from VIL (DC) for a rising signal and VIH (DC) for a falling signal. If the differential DQS slew rate is not equal to 2 V/ns, then the baseline values must be derated. If the DQS differential strobe feature is not enabled, then the DQS strobe is single-ended, the baseline values not applicable, and timing is not referenced to the logic trip points. Singleended DQS data timing is referenced to DQS crossing VREF. 8. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (tHZ) or begins driving (tLZ). 9. This maximum value is derived from the referenced test load. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. 10. tLZ (MIN) will prevail over a tDQSCK (MIN) + tRPRE (MAX) condition 11. The intent of the "Don't Care" state after completion of the postamble is the DQSdriven signal should either be high, low or High-Z and that any signal transition within the input switching region must follow valid input requirements. That is if DQS transitions high (above VIHDC(min) then it must not transition low (below VIH(DC) prior to tDQSH(min). 12. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 13. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 14. The refresh period is 64ms (commercial) or 32ms (industrial). This equates to an average refresh rate of 7.8125s (commercial) or 3.9607s (industrial). However, a REFRESH command must be asserted at least once every 70.3s or tRFC (MAX).
March 2006 Rev. 0 10
21.
22. 23.
24.
25. 26. 27. 28.
29.
30. 31. 32.
33. 34. 35.
36.
To ensure all rows of all banks are properly refreshed, 8,192 REFRESH commands must be issued every 64ms. Referenced to each output group: x4 = DQS with DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 = LDQS with DQ0-DQ7; and UDQS with DQ8-DQ15. CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if measured differentially). The data valid window is derived by achieving other specifications - tHP. (tCK/2), t DQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. READs and WRITEs with auto precharge are allowed to be issued before t RAS(MIN) is satisfied since tRAS lockout feature is supported in DDR2 SDRAM. VIL/VIH DDR2 overshoot/undershoot. t DAL = (nWR) + (tRP/tCK). Each of these terms, if not already an integer, should be rounded up to the next integer. tCK refers to the application clock period; nWR refers with tWR programmed to four clocks would have tDAL = 4 + (15ns/3.75ns) clocks = 4 + (4) clocks = 8 clocks. The minimum internal READ to PRECHARGE time. This is the time from the last 4-bit prefetch begins to when the PRECHARGE command can be issued. A 4-bit prefetch is when the READ command internally latches the READ so that data will output CL later. This parameter is only applicable when tRTP/(2x tCK) > 1, such as frequencies faster than 533 MHz when tRTP = 7.5ns. If tRTP/ (2x tCK) 1, then equation AL + BL/2 applies. tRAS (MIN) also has to be satisfied as well. The DDR2 SDRAM will automatically delay the internal PRECHARGE command until tRAS (MIN) has been satisfied. Operating frequency is only allowed to change during self refresh mode, precharge power-down mode, and system reset condition. t DAL = (nWR) + (tRP/tCK): For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period; AC Operation Condition Notes: nWR refers to the tWR parameter stored in the MR[11,10,9]. Example: For -533Mb/s at tCK = 3.75 ns with tWR programmed to four clocks. tDAL = 4 + (15 ns/3.75 ns) clocks = 4 +(4) clocks = 8 clocks. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance. ODT turn off time tAOF (MAX) is when the bus is in high-Z. Both are measured from t AOFD. This parameter has a two clock minimum requirement at any tCK. t DELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed prior to CK, CK# being removed in a system RESET condition. t ISXR is equal to tIS and is used for CKE setup time during self refresh exit. No more than 4 bank ACTIVE commands may be issued in a given tFAW(min) period. tRRD(min) restriction still applies. The tFAW(min) parameter applies to all 8 bank DDR2 devices, regardless of the number of banks already open or closed. t RPA timing applies when the PRECHARGE(ALL) command is issued, regardless of the number of banks already open or closed. If a single-bank PRECHARGE command is issued, tRP timing applies. tRPA(MIN) applies to all 8-bank DDR2 devices. Value is minimum pulse width, not the number of clock registrations. This is applicable to Read cycles only. Write cycles generally require additional time due to tWR during auto precharge. t CKE (MIN) of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. This parameter is not referenced to a specific voltage level, but specified when the device output is no longer driving (tRPST) or beginning to drive (tRPRE). When DQS is used single-ended, the minimum limit is reduced by 100ps. The half-clock of tAOFD's 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock value must be derated by the amount of half-clock duty cycle error. For example, if the clock duty cycle was 47/53, tAOFD would actually be 2.5 - 0.03, or 2.47 for tAOF (MIN) and 2.5 + 0.03 or 2.53 for tAOF (MAX). The clock's tCKAVG is the average clock over any 200 consecutive clocks and
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t CKAVG(MIN) is the smallest clock rate allowed, except a deviation due to allowed clock jitter. Input clock jitter is allowed provided it does not exceed values specified. Also, the jitter must be of a random Gaussian distribution in nature. The inputs to the DRAM must be aligned to the associated clock; that is, the actual clock that latches it in. However, the input timing (in ns) references to the tCKAVG when determining the required number of clocks. The following input parameters are determined by taking the specified percentage times the tCKAVG rather thank tCK: t IPW, tDIPW, tDQSS, tDQSH, tDQSL, tDSS, tDH, tWPST, and tWPRE. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate spread spectrum at a sweep rate in the range 20-60 KHz with additional one percent of tCKAVG as a long-term jitter component; however, the spread spectrum may not use a clock rate below tCKAVG(MIN) or above t CKAVG(MAX). The period jitter (tJITPER) is the maximum deviation in the clock period from the average or nominal clock allowed in either the positive or negative direction. JEDEC specifies tighter jitter numbers during DLL locking time. During DLL lock time, the jitter values should be 20 percent less than noted in the table (DLL locked). The half-period jitter (tJITDTY) applies to either the high pulse of clock or the low pulse of clock; however, the two cumulatively can not exceed tJITPER. The cycle-to-cycle jitter (tJITCC) is the amount the clock period can deviate from one cycle to the following cycle. JEDEC specifies tighter jitter numbers during DLL locking time. During DLL lock time, the jitter values should be 20 percent less than noted in the table (DLL locked). The cumulative jitter error (tERRnPER) where n is 2, 3, 4, 5, 6-10, or 11-50, is the amount of clock time allowed to consecutively accumulate away from the average clock over any number of clock cycles. The DRAM output timing is aligned to the nominal or average clock. Most output
W3HG128M64EEU-D4
ADVANCED*
37.
38.
44.
39.
45.
40. 41.
46. 47.
42.
48. 49.
43.
parameters must be derated by the actual jitter error when input clock jitter is present; this will result in each parameter becoming larger. The following parameters are required to be derated by subtracting tERR5PER(MAX): tAC(MIN), tDQSCK(MIN), t HZ(MIN), tLZDQ(MIN), tAON(MIN); while these following parameters are required to be derated by subtracting tERR5PER(MIN): tAC(MAX), tDQSCK(MAX), tHZ(MAX), t LZDQ(MAX), tAON(MAX). The parameter tRPRE(MIN) is derated by subtracting t JITPER(MAX), while tPRPE(MAX), is derated by subtracting tJITPER(MAX) . The parameter tRPST(MAX), is dated by subtracting tJITDTY(MIN). Half-clock output parameters must be derated by the actual tERR5PER and tJITDTY when input clock jitter is present; this will result in each parameter becoming larger. The parameter tAOF(MIN) is required to be derated by subtracting both t ERR5PER(MAX) and tJITPER(MAX). The parameter tAOF(MAX) is required to be derated by subtracting both tERR5PER(MIN) and tJITDTY(MIN). MIN(tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time driven to the device. The clock's half period must also be of a Gaussian distribution; tCHAVG and tCLAVG must be met with or with our clock jitter and with or without duty cycle jitter. tCHAVG and tCLAVG are the average of any 200 consecutive CK falling edges. t HP (MIN) is the lesser of tCL and tCH actually applied to the device CK and CK# inputs; thus, tHP(MIN) the lesser of tCLABS(MIN) and tCHABS(MIN). t QH = tHP - tQHS; the worst case tQH would be the smaller of tCLABS(MAX) or t CHABS(MAX) times tCKABS(MIN) - tQHS. Minimizing the amount of tCHAVG offset and value of tJITDTY will provide a larger tQH, which in turn will provide a larger valid data out window. JEDEC specifies using tERR6-10PER when derating clock-related output timing (notes 43-44). Micron requires less derating by allowing tERR5PER to be used. Requires 8 tCK for backward compatibility.
March 2006 Rev. 0
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Clock/Data Rate Frequency 400MHz/800Mb/s 333MHz/667Mb/s 266MHz/533Mb/s 200MHz/400Mb/s CAS Latency 6 5 4 3
W3HG128M64EEU-D4
ADVANCED
ORDERING INFORMATION FOR D4
Part Number W3HG128M64EEU806D4xxG** W3HG128M64EEU665D4xxG* W3HG128M64EEU534D4xxG W3HG128M64EEU403D4xxG
** Consult Factory for availability NOTES: * RoHS product. ("G" = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
tRCD 6 5 4 3
tRP 6 5 4 3
Height* 29.20mm (1.150") TYP 29.20mm (1.150") TYP 29.20mm (1.150") TYP 29.20mm (1.150") TYP
PACKAGE DIMENSIONS FOR D4
FRONT VIEW
67.75 (2.667) MAX 2.00 (0.079) R (2X) 1.80 (0.071) (2X) 3.80 (0.150) MAX
29.20 (1.150) TYP 20.00 (0.787) TYP
6.00 (0.236) 2.54 (0.100) 1.10 (0.043) MAX 0.45 (0.018) TYP 0.60 (0.024) TYP
2.15 (0.085)
0.99 (0.039) TYP
PIN 199
PIN 1
63.60 (2.504) TYP
BACK VIEW
PIN 200
47.4 (1.87) TYP
4.2 (0.165) TYP 11.4 (0.45) TYP
PIN 2
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
March 2006 Rev. 0 12 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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PART NUMBERING GUIDE
W3HG128M64EEU-D4
ADVANCED
W 3 H G 128M 64 E E U xxx D4 x x G
WEDC MEMORY (SDRAM) DDR 2 GOLD DEPTH BUS WIDTH COMPONENT WIDTH x8 1.8V UNBUFFERED DATA RATE (Mb/s) PACKAGE 200 PIN INDUSTRIAL TEMP OPTION (For commercial leave "blank" for industrial add "I") COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT
March 2006 Rev. 0
13
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Document Title
1GB - 128Mx64 DDR2 SDRAM UNBUFFERED
W3HG128M64EEU-D4
ADVANCED
DRAM DIE OPTIONS: * SAMSUNG: A-Die, will move to B-Die Q3'06 * MICRON: U38A:A, will move to U38Z:D Q4'06, and U48B:E Q2'07
Revision History Rev #
Rev 0 Rev 1
History
Created 1.0 Update part number guide 1.2 Added indicator "x" in part number for industrial temp option 1.3 Added DRAM die option
Release Date
3-06 4-06
Status
Advanced Advanced
March 2006 Rev. 0
14
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